A problem which is inherent in the p-well and n-well processes is due to the relatively large number of junctions which are formed in these structures and, as mentioned earlier, the consequent presence of parasitic transistors and diodes. Latch-up is a condition in which the parasitic components give rise to the establishment of low-resistance conducting paths between Vdd and Vss with disastrous results. Careful control during fabrication is necessary to avoid this problem.
An improved BICMOS inverter using MOS transistors for base
current discharge.
Latch-up may be induced by glitches on the supply rails or by incident radiation. The mechanism involved may be understood by the key parasitic components associated with a p-well structure in which an inverter circuit has formed.
Latch-up effect in p-well structure.
There are, in effect, two transistors and two resistances (associated with the p-well and with regions of the substrate) which form a path between Vdd and Vss. If sufficient substrate current flows to generate enough voltage across Rs to turn on transistor T1, this will then draw current through Rp and if the voltage developed is sufficient, T2 will also turn on, establishing a self-sustaining low-resistance path between the supply rails. If the current gains of the two transistors are such that β1 × β2 >1, latch-up may occur.
Latch-up circuit model.
With no injected current, the parasitic transistors will exhibit high resistance, but sufficient substrate current flow will cause switching to the low-resistance state as already explained. The switching characteristic of the arrangement is outlined as below
Latch-up current versus voltage.
Once latched-up, this condition will be maintained until the latch-up current drops below Il. It is this essential for a CMOS process to ensure that Vl and Il
Remedies for the latch-up problem include:
- An increase in substrate doping levels with a consequent drop in the value of Rs;
- Reducing Rp by control of fabrication parameters and by ensuring a low contact resistance to Vss;
- Other more elaborate measures such as the introduction of guard rings.
Latch-up circuit for n-well process.
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