Latch-Up in CMOS circuits

                          A problem which is inherent in the p-well and n-well processes is due to the relatively large number of junctions which are formed in these structures and, as mentioned earlier, the consequent presence of parasitic transistors and diodes. Latch-up is a condition in  which the parasitic components give rise to the establishment of low-resistance conducting paths between Vdd and Vss with disastrous results. Careful control during fabrication is necessary to avoid this problem.

An improved BICMOS inverter using MOS transistors for base

current discharge.

                          Latch-up may be induced by glitches on the supply rails or by incident radiation. The mechanism involved may be understood by the key parasitic components associated with a p-well structure in which an inverter circuit has formed.

Latch-up effect in p-well structure.

                            There are, in effect, two transistors and two resistances (associated with the p-well and with regions of the substrate) which form a path between Vdd and Vss. If sufficient substrate current flows to generate enough voltage across Rs to turn on transistor T1, this will then draw current through Rp and if the voltage developed is sufficient, T2 will also turn on, establishing a self-sustaining low-resistance path between the supply rails. If the current gains of the two transistors are such that β₁ × β₂ >1, latch-up may occur.

Latch-up circuit model.

                           With no injected current, the parasitic transistors will exhibit high resistance, but sufficient substrate current flow will cause switching to the low-resistance state as already explained. The switching characteristic of the arrangement is outlined as below

Latch-up current versus voltage.

                           Once latched-up, this condition will be maintained until the latch-up current drops below I_l. It is this essential for a CMOS process to ensure that V_l and I­_l are not readily achieved in any normal mode of operation.

                          

      Remedies for the latch-up problem include:

1. An increase in substrate doping levels with a consequent drop in the value of R_s;
2. Reducing R_p by control of fabrication parameters and by ensuring a low contact resistance to V_ss;
3. Other more elaborate measures such as the introduction of guard rings.

                           

Latch-up circuit for n-well process.

1. D.S. Yaney and CW. Pearce, IEDM-81 Technical Digest, 1981, pp. 236-239.

2. D. Takacs, J. Harter, E.P. Jacobs, C Werner, U. Schwabe, J. Winnerl and E. Lange, IEDM-83 Technical Digest, 1983,pp.159-163.

3. Y. Sakai, T. Hayashida, N. Hashimoto, O. Mimato, T. Masahara, K. Nagasawa, T. Yasai. and N. Tanimura. IEDM-81 Technical Digest, 1981, pp. 534-537.

4. J.O. Borland and R.S. Singh, 5th International Conference on Solid State Devices and Materials, Japan Society of Applied Physics, August 1984, pp. 487-490.

5. W. Dyson, S.O. Grady, J.A. Rossi, L.G. Helliwig and J.W. Moody, "VLSI Science and Technology," ECS PV84-7, K. Bean and G.A. Rozgonyi, eds., The Electrochemical Society, 1984, pp. 107-119.

6. CW. Pearce and G.A. Rozgonyi, "VLSI Science and Technology," ECS PV82-7, CJ. Dell'Oca and W.M. Bullis, eds.. The Electrochemical Society, 1982, pp. 53-59.

7. D. Estreich and R. Dutton, IEEE Transactions on Computer-Aided Design, vol. CAD-I, no. 4, October 1982, pp. 157-162. ©Applied Materials, Inc. 1985

8. D. Estreich, Technical Report No. G-201-9, Stanford University, November 1980.

9. J.O. Borland and T. Deacon, Solid State Technology, vol. 27, no. 8, August 1984, pp.123-131.

10. B.L. Gregory and B.D. Shafer, IEEE Trans. Nucl. Sci., vol. NS-20, December 1973, pp. 293-299.

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13. J.O. Borland, "Defects in Silicon," ECS PV83-9, W.M. Bullis and L.C Kimerling, eds., The Electrochemical Society, 1983, pp.194-203.

VLSI System design cycle

System Design Cycle : Usually the design process for any system components has to be performed at algorithm level, architectural level, logical level and circuit layout level. For example conceptual model of arithmetic processor design as shown below follows steps needed to arrive from fundamental problem at hand to the realization of the physical layout, with low power and minimum area being important design criterion.

VLSI design cycle start with a formal specification of a VLSI chip, follows a series of steps, and eventually produces a packaged chip.

A simple VLSI design cycle: 

System Specification 

Functional design 

Logic design 

Circuit design 

Physical design 

Fabrication 

Packaging, Testing and Debugging 

VLSI DESIGN CYCLE

System Specification: 

1. First step of design process is to lay down the specification of the system.
2. High level representation of the system.
3. Factors considered:
       a) Performance
       b) Functionality
       c) Physical dimension
       d) Design technique
       e) Fabrication technology
4. It is a compromise between market requirements, technological and economical viability.

The end results are specifications of 

1. Size
2. Speed
3. Power and
4. Functionality of the VLSI system
5. Basic architecture of the system are also specified, such as
        a)  Floating point unit
        b)  RISC versus CISC system
        c)  Number of ALU's
        d)  Number and structure of the pipelines
        e)  Size of the cache, etc.

Functional Design:

1. Main functional units of the system are identified.
2. Identifies the interconnect requirements between the units.
3. The area, power and other parameters of each unit are estimated.
4. The behavioral aspects of the system are considered not implementation specification.
       - multiplication needed but does not specify its hardware.
5. The key idea is to specify behavior, in terms of
        a)  Input
        b)  Output
        c)  Timing of each unit
     without specifying the internal structure.
6. The outcome of functional design is usually a timing diagram or other relationships between units.
7. This information leads to improvement of the overall design process and reduction of complexity of the subsequent phases.
8. Functional design provides a quick emulation of the system and allows fast debugging of the full system.

Logic Design: 

Design the logic, that is,

1. Boolean expressions,
2. Control flow,
3. Word width,
4. Register allocation, etc.

The outcome is called an RTL(Register Transfer Level) description. RTL is expressed in a HDL(Hardware Description Language), such as VHDL and Verilog.

This description can be used in simulation and verification.

As this description consists of Boolean expressions, so they can be minimized to achieve the smallest logic design. 

Circuit Design: 

1. The purpose of the circuit design is to develop a circuit representation based on the logic design.
2. The Boolean expression can be converted into a circuit representation by taking into consideration the speed and power requirements of the original design.
3. Design the circuit including gates, transistors, interconnections, etc. The outcome is called a netlist.
4. Circuit simulation is used to verify the correctness and timing of component.

Physical Design:

1. The circuit representation of each component is converted into geometric representation.
2. Convert the netlist into a geometric representation. The outcome is called layout.
3. Connections between different components are also expressed as a geometric pattern.
4. Exact details depends upon design rules
5. It is a complex process and usually broken down into sub-steps.
6. Various verification and validation checks are performed on the layout during physical design.

Fabrication:

1. Process includes lithography, polishing, deposition, diffusion, etc., to produce a chip.
2. Fabrication process consists of several steps and requires various masks.
3. Before the chip is mass produced, a prototype is made and tested.

Packaging: 

1. Put together the chips on a PCB(Printed Circuit Board) or an MCM(Multi-Chip Module)
2. Each chip is then packaged and tested to ensure that it meets all the design specifications and that it functions properly.